A Dynamic Random Access Memory (DRAM) is a memory device constructed of a collection of cells each made up of a transistor and a capacitor. DRAM cells are arranged in a matrix with multiple rows and columns of cells. Each row of cells is referred to as a “page” and the matrix of DRAM cells is referred to as a “bank.” Multiple banks are combined to form a DRAM device. DRAM operates to retain information in each cell by storing a charge in the capacitor and using the transistor as an access switch. The capacitor may either be charged or discharged corresponding to a stored value of, for example, 1 or 0. A write to a location of either a “0” or a “1” may be considered a “refresh” in that the value will be maintained for the duration of the refresh cycle in which the value was written. For example, if a page is written to, the page may be considered refreshed for the duration of the refresh cycle.
Over time, the capacitor eventually “leaks”, or loses its charge, requiring the DRAM to be periodically refreshed. A value for the capacitor drain time, that is, the time it takes for the capacitor to fully lose a charge, is around 64 ms depending on systematic factors such as temperature and other factors. Sometime before the discharge time elapses, a refresh should occur to sustain the charge state of charged cells.
Refresh may be accomplished by performing a refresh command (REF) provided by the DRAM manufacturer and may be periodically issued by, for example, the memory controller on a System-on-Chip (SoC) within which the DRAM is embedded or to which the DRAM is coupled. The REF command does not require the address of the page. Instead, when the REF command is issued, the address for refresh is computed internally within the DRAM based on the operation of internal logic. During a typical refresh associated with the REF command, a single page in the entire DRAM is refreshed (per bank refresh), or one page in every bank in the DRAM is refreshed (all bank refresh). During the REF refresh operation, or any refresh operation, the bank containing the page undergoing refresh is unavailable for access. For an all bank refresh, the entire DRAM becomes unavailable.
Unavailability of the DRAM during refresh negatively impacts DRAM access performance. Rather than iteratively refreshing all the pages at the same time, which would result in a refresh of the entire DRAM and complete unavailability for access, the refresh command is applied over the 64 ms period to different sections of the DRAM. Accordingly, for a refresh of an entire DRAM on a page by page basis, each page is refreshed within the 64 ms and only one page, or one page in all banks, is unavailable at one time. By spreading out the refresh command in the above described manner, more refresh commands are issued. The page refresh interval becomes 3.9 us or 7.8 us, depending on the density and architecture of the memory. For example for a DRAM with 8K (8192, or 213) pages, the page refresh interval may be calculated as: tREFI=64 ms/8192=7.8 us. A conventional DRAM has internal logic that tracks the page(s) that are to be refreshed next. Internal logic in the device may be configured to iterate through all of the pages in a sequential manner. The memory controller may issue the REF command every tREFI as defined by the DRAM manufacturer. To reduce the impact of REF on DRAM performance, DRAM vendors may internally refresh two or more pages at a time. The conventional REF command provided by DRAM vendors is not configured to accept an address associated with a page location or multiple addresses for multiple locations. Therefore, a system designer has little flexibility to control aspects of the DRAM refresh operation. As a result, potential efficiency gains that would be achievable if DRAM refresh was controllable are not able to be realized.